In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. As the size of the individual circuit elements is reduced, so is the available real estate for conductive interconnects in integrated circuits. Consequently, these interconnects have to be reduced to compensate for a reduced amount of available real estate and for an increased number of circuit elements provided per chip.
Generally, integrated circuits (ICs) comprise electronic components, such as transistors, capacitors, or the like, formed on a substrate. One or more metal layers are then formed over the electronic components to provide connections between the electronic components and to provide connections to external devices. The metal layers typically comprise an inter-layer dielectric (ILD) layer in which vias and interconnects are formed, usually with a single- or dual-damascene process.
As mentioned above, the trend in the semiconductor industry is towards the miniaturization or scaling of integrated circuits, in order to provide smaller ICs and improve performance, such as increased speed and decreased power consumption. While aluminum and aluminum alloys were most frequently used in the past for the material of conductive lines in integrated circuits, the current trend is to use copper for a conductive material because copper has better electrical characteristics than aluminum, such as decreased resistance, higher conductivity, and a higher melting point.
The change in the conductive line material and insulating materials of semiconductor devices has introduced new challenges in the manufacturing process. FIG. 1 illustrates a portion of a wafer 100 having an ideal interconnect structure. Generally, the wafer 100 comprises a substrate 110, which may have electronic components such as transistors, capacitors, or the like formed thereon, or may comprise a metallization layer. An etch stop layer 112 is formed on the substrate 110, and a dielectric layer 114 is formed on the etch stop layer 112. A trench 116 and via 118 are formed through the dielectric layer 114 and the etch stop layer 112. The trench 116 and the via 118 are typically lined with a barrier/adhesion layer 120 (such as tantalum nitride) and then filled with a conductive material (such as copper).
FIG. 2 illustrates a common problem that may occur with an interconnect structure such as that illustrated in FIG. 1. In particular, the conductive material used to fill the trench 116 and the via 118 may exert a tensile stress, causing the conductive material to pullback from the bottom of the via and creating a pullback void 210. The pullback void 210 may increase the contact resistance between the interconnect structure and the underlying electrical component, or even cause the device to fail. This is particularly a problem when using copper as the conductive material to fill the trench 116 and the via 118.
Accordingly, there is a need for an interconnect structure that allows for the use of a low resistance material, such as copper, and prevents or reduces the pullback void.